1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same. More particularly, the present invention relates to a single electron transistor having a memory function and a method of manufacturing the single electron transistor.
2. Description of the Related Art
In memory devices comprised of a quantum dot junction or a single electron junction having a size of 0.1 nm or less, the movement of an individual electron may be controlled by adjusting an external source voltage. This is called a single electron effect. A transistor using the single electron effect is referred to as a single electron transistor (SET).
An SET is comprised of a nano-sized quantum dot formed between a source and a drain and a gate electrode electrocapacitively coupled to the quantum dot.
Referring to FIG. 1, in a conventional single electron transistor, a gate electrode 16 is formed on a predetermined area of an insulation layer 10. Portions of predetermined thicknesses of the insulation layer 10 are removed from both sides of the gate electrode 16, and first and second conductive films 20 and 22 are formed on the resultant empty spaces formed by the removal of portions of the insulation layer 10. A source region 12 exists in a portion of the insulation layer 10 under the first conductive film 20, and a drain region 14 exists in a portion of the insulation layer 10 under the second conductive film 22. The source and drain regions 12 and 14 each extend to respective areas under the gate electrode 16. A quantum dot 18, in which an electron (e) is trapped, exists in a portion of the insulating layer 10 under the gate electrode 16 between the source and the drain regions 12 and 14.
The single electron transistor of FIG. 1 has a practical difficulty in uniformly forming the quantum dots 18 at accurate locations, thus resulting in low reproducibility.
To solve these problems, various types of single electron transistors have been developed. A cross-sectional view of one type of a single electron transistor is illustrated in FIG. 2.
Referring to FIG. 2, an oxide film 32 exists on a substrate 30, and a silicon layer 34 exists on the oxide film 32. The silicon layer 34 is comprised of a source region 34a, a channel region 34b, and a drain region 34c. A quantum dot 34d is formed in the channel region 34b. Nitride films 36a and 36b are symmetrically placed with respect to the quantum dot 34d and are located over the silicon layer 34, but are isolated from the silicon layer 34 by a portion of an interlayer insulation film 42. The quantum dot 34d is formed by charging the nitride films 36a and 36b with electrons. Polysilicon depletion gates 38a and 38b exist in the form of spacers at facing ends of the nitride films 36a and 36b, respectively. The depletion gates 38a and 38b are isolated from each other by a distance corresponding to the size of quantum dot 34d. A polysilicon control gate 40 exists over the nitride films 36a and 36b but is isolated from the nitride films 36a and 36b and the polysilicon depletion gates 38a and 38b by another portion of the interlayer insulation film 42. A portion of the control gate 40, which exists between the depletion gates 38a and 38b, protrudes downwards toward the quantum dot 34d. The space between the silicon layer 34 and the control gate 40 and the nitride films 36a and 36b and the polysilicon depletion gates 38a and 38b is filled with the interlayer insulation film 42.
As described above, because the quantum dot 34d of the conventional single electron transistor of FIG. 2 is formed by charging the nitride films 36a and 36b with electrons, the conventional single electron transistor of FIG. 2 has a degree of reproducibility related to a single electron effect. However, since the conventional single electron transistor of FIG. 2 includes two or more gates, such as the depletion gates 38a and 38b and the control gate 40, excessive power is consumed, and an operational circuit and a manufacturing process of the conventional single electron transistor are complicated.